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| dm9010 single chip ethernet controller with general processor interface preliminary 1 version: dm9010-ds-p03 apr. 28, 2005 davicom semiconductor, inc. dm9010 10/100 mbps single chip ethernet controller with general processor interface data sheet preliminary version: dm9010-ds-p03 apr. 28 2005
dm9010 single chip ethernet controller with general processor interface preliminary 2 version: dm9010-ds-p03 apr. 28, 2005 content 1. general description................... ...................................................................................... ..................................... 7 2. block diagram............................................................................................................... ............................................ 7 3. features.................................................................................................................... ..................................................... 8 4. pin configuration........................................................................................................... ......................................... 9 4.1 p in c onfiguration i: with mii i nterface ................................................................................................................. 9 4.2 p in c onfiguration ii: with 32-b it d ata b us ......................................................................................................... 10 5. pin description.......................... ................................................................................... ............................................ 11 5.1 mii i nterface ............................................................................................................................... .............................. 11 5.2 p rocessor i nterface ............................................................................................................................... ................. 12 5.3 eeprom i nterface ............................................................................................................................... .................... 13 5.4 c lock i nterface ............................................................................................................................... ......................... 13 5.5 led i nterface ............................................................................................................................... ............................ 13 5.6 10/100 phy/f iber ............................................................................................................................... ........................ 14 5.7 m iscellaneous ............................................................................................................................... ........................... 14 5.8 p ower p ins ............................................................................................................................... ................................... 14 5.9 strap pins table ............................................................................................................................... .......................... 15 6. vendor control and status register set...................................................................................... ........ 15 6.1 n etwork c ontrol r egister (00h).......................................................................................................................... 17 6.2 n etwork s tatus r egister (01h) .......................................................................................................................... ... 17 6.3 tx c ontrol r egister (02h) .......................................................................................................................... ........... 18 6.4 tx s tatus r egister i ( 03h ) for packet index i.................................................................................................... 18 6.5 tx s tatus r egister ii ( 04h ) for packet index i i ................................................................................................ 18 6.6 rx c ontrol r egister ( 05h ) .............................................................................................................................. ..... 19 6.7 rx s tatus r egister ( 06h ) .............................................................................................................................. ........ 19 6.8 r eceive o verflow c ounter r egister ( 07h )........................................................................................................ 19 6.9 b ack p ressure t hreshold r egister (08h) ............................................................................................................ 20 6.10 f low c ontrol t hreshold r egister ( 09h ) ......................................................................................................... 20 6.11 rx/tx f low c ontrol r egister ( 0ah )................................................................................................................ 20 dm9010 single chip ethernet controller with general processor interface preliminary 3 version: dm9010-ds-p03 apr. 28, 2005 6.12 eeprom & phy c ontrol r egister ( 0bh ) ......................................................................................................... 21 6.13 eeprom & phy a ddress r egister ( 0ch ).......................................................................................................... 21 6.14 eeprom & phy d ata r egister (ee_phy_l j 0dh ee_phy_h j 0eh) ...................................................... 21 6.15 w ake u p c ontrol r egister ( 0fh )....................................................................................................................... 21 6.16 p hysical a ddress r egister ( 10h~15h ) .............................................................................................................. 22 6.17 m ulticast a ddress r egister ( 16h~1dh ) .......................................................................................................... 22 6.18 g eneral purpose control r egister ( 1eh ) ...................................................................................................... 22 6.19 g eneral purpose r egister ( 1fh )......................................................................................................................... 22 6.20 tx sram r ead p ointer a ddress r egister (22h~23h)...................................................................................... 23 6.21 rx sram w rite p ointer a ddress r egister (24h~25h) .................................................................................... 23 6.22 v endor id r egister (28h~29h)...................................................................................................................... ....... 23 6.23 p roduct id r egister (2ah~2bh)...................................................................................................................... .... 23 6.24 c hip r evision r egister (2ch) .......................................................................................................................... ...... 23 6.25 t ransmit c ontrol r egister 2 ( 2dh ) .................................................................................................................. 23 6.26 o peration t est c ontrol r egister ( 2eh )........................................................................................................... 24 6.27 s pecial m ode c ontrol r egister ( 2fh ) .............................................................................................................. 24 6.28 e arly t ransmit c ontrol /s tatus r egister ( 30h )............................................................................................. 24 6.29 t ransmit c heck s um c ontrol r egister ( 31h ).................................................................................................. 25 6.30 r eceive c heck s um c ontrol s tatus r egister ( 32h ) ....................................................................................... 25 6.31 e xternal phy ceiver a ddress r egister ( 33h ) ............................................................................................... 25 6.32 g eneral p urpose c ontrol r egister 2 ( 34h ) ................................................................................................... 25 6.33 g eneral p urpose r egister 2 ( 35h )............................................................................................................... 26 6.34 g eneral p urpose c ontrol r egister 3 ( 36h ) ................................................................................................... 26 6.35 g eneral p urpose r egister 3 ( 37h )............................................................................................................... 26 6.36 m onitor r egister 1 ( 40h ).............................................................................................................................. ....... 26 6.37 m onitor r egister 2 ( 41h ).............................................................................................................................. ....... 26 6.38 m emory d ata p re -f etch r ead c ommand without a ddress i ncrement r egister (f0h) ............................. 27 6.39 m emory d ata r ead c ommand without a ddress i ncrement r egister (f1h) ................................................ 27 6.40 m emory d ata r ead c ommand with a ddress i ncrement r egister (f2h)....................................................... 27 6.41 m emory d ata r ead _ address r egister (f4h~f5h)............................................................................................ 27 6.42 m emory d ata w rite c ommand without a ddress i ncrement r egister (f6h) .............................................. 27 6.43 m emory data write comman d with address increment r egister (f8h)........................................................ 27 6.44 m emory data write _ address r egister (fah~fbh).......................................................................................... 27 6.45 tx p acket l ength r egister (fch~fdh)............................................................................................................. 27 dm9010 single chip ethernet controller with general processor interface preliminary 4 version: dm9010-ds-p03 apr. 28, 2005 6.46 i nterrupt s tatus r egister (feh) ......................................................................................................................... 2 8 6.47 i nterrupt m ask r egister (ffh).......................................................................................................................... .. 28 7. eeprom format............................................................................................................... ......................................... 29 8. mii register description .......... .......................................................................................... ............................... 30 8.1 b asic m ode c ontrol r egister (bmcr) - 00 .......................................................................................................... 31 8.2 b asic m ode s tatus r egister (bmsr) - 01.............................................................................................................. 32 8.3 phy id i dentifier r egister #1 (phyid1) - 02 ........................................................................................................ 34 8.4 phy id i dentifier r egister #2 (phyid2) - 03 ........................................................................................................ 34 8.5 a uto - negotiation a dvertisement r egister (anar) - 04 ................................................................................... 34 8.6 a uto - negotiation l ink p artner a bility r egister (anlpar) ? 05................................................................... 35 8.7 a uto - negotiation e xpansion r egister (aner)- 06 ............................................................................................. 36 8.8 davicom s pecified c onfiguration r egister (dscr) - 16................................................................................. 37 8.9 davicom s pecified c onfiguration and s tatus r egister (dscsr) - 17.......................................................... 38 8.10 10base-t c onfiguration /s tatus (10btcsr) - 18.............................................................................................. 39 8.11 p ower d own c ontrol r egister (pwdor) - 19 ................................................................................................... 40 8.12 (s pecified config ) r egister ? 20 ............................................................................................................................ 4 1 9. functional description............ .......................................................................................... ............................... 42 9.1 h ost i nterface ............................................................................................................................... ........................... 42 9.2 d irect m emory a ccess c ontrol ............................................................................................................................ 42 9.3 p acket t ransmission ............................................................................................................................... ................. 42 9.4 p acket r eception ............................................................................................................................... ....................... 42 9.5 100b ase -tx o peration ............................................................................................................................... .............. 43 9.5.1 4b5b encoder ............................................................................................................. ......................................... 43 9.5.2 scrambler ................................................................................................................ ............................................. 43 9.5.3 parallel to serial converter. ............................................................................................ .................................... 43 9.5.4 nrz to nrzi encoder ...................................................................................................... .................................... 43 9.5.5 mlt-3 converter .......................................................................................................... ....................................... 43 9.5.6 mlt-3 driver............................................................................................................. .......................................... 43 9.5.7 4b5b code group .......................................................................................................... ...................................... 44 9.6 100b ase -tx r eceiver ............................................................................................................................... ................ 45 9.6.1 signal detect ............................................................................................................ ............................................ 45 9.6.2 adaptive equalization ................. .......................... .......................... ................... ............ ...................................... 45 dm9010 single chip ethernet controller with general processor interface preliminary 5 version: dm9010-ds-p03 apr. 28, 2005 9.6.3 mlt-3 to nrzi decoder .................................................................................................... .................................. 45 9.6.4 clock recovery module .................................................................................................... ................................... 45 9.6.5 nrzi to nrz .............................................................................................................. .......................................... 45 9.6.6 serial to parallel....................................................................................................... ........................................... 45 9.6.7 descrambler.............................................................................................................. ........................................... 45 9.6.8 code group alignment ..................................................................................................... ................................... 46 9.6.9 4b5b decoder ............................................................................................................. ......................................... 46 9.7 10b ase -t o peration ............................................................................................................................... ................... 46 9.8 c ollision d etection ............................................................................................................................... .................. 46 9.9 c arrier s ense ............................................................................................................................... ............................. 46 9.10 a uto -n egotiation ............................................................................................................................... ................... 46 9.11 p ower r educed m ode ............................................................................................................................... .............. 47 9.11.1 power down mode......................................................................................................... .................................... 47 9.11.2 reduced transmit power mode ............................................................................................. ............................ 47 10. dc and ac electrical characteristi cs ..................... .......................... ...................... .................. .......... 48 10.1 a bsolute m aximum r atings ............................................................................................................................... .. 48 10.1.1 operating conditions.......... .......................................................................................... ..................................... 48 10.2 dc e lectrical c haracteristics (vdd = 3.3v) ................................................................................................... 48 10.3 ac e lectrical c haracteristics & t iming w aveforms ..................................................................................... 49 10.3.1 tp interface ............................................................................................................................... ......................... 49 10.3.2 oscillator/crystal timing ............................................................................................................................... ... 49 10.3.3 processor i/o read timing............................................................................................... ................................. 49 10.3.4 processor i/o write timing .............................................................................................. ................................. 50 10.3.5 external mii interface transmit timing .................................................................................. .......................... 51 10.3.6 external mii interface receive timing ...................... ......................... ........................ ............ ........................... 51 10.3.7 mii management interface timing ......................................................................................... ........................... 52 10.3.8 eeprom interface timing . .......................... ......................... .......................... ................... ............................... 52 11. application notes.......................................................................................................... ...................................... 53 11.1 n etwork i nterface s ignal r outing .................................................................................................................... 53 11.2 10b ase -t/100b ase -tx a uto mdix a pplication ................................................................................................. 53 11.3 10b ase -t/100b ase -tx ( n on a uto mdix t ransformer a pplication )............................................................ 54 11.4 p ower d ecoupling c apacitors ............................................................................................................................. 55 dm9010 single chip ethernet controller with general processor interface preliminary 6 version: dm9010-ds-p03 apr. 28, 2005 11.5 g round p lane l ayout ............................................................................................................................... ............ 56 11.6 p ower p lane p artitioning ............................................................................................................................... ...... 57 11.7 m agnetics s election g uide ............................................................................................................................... ... 58 11.8 c rystal s election g uide ............................................................................................................................... ............. 58 11.9 a pplication of reverse mii ............................................................................................................................ ............. 59 12. package information............... ......................................................................................... ................................ 60 13. ordering information ............................................................................................................................... ........... 61 dm9010 single chip ethernet controller with general processor interface preliminary 7 version: dm9010-ds-p03 apr. 28, 2005 1. general description the dm9010 is a fully integrated and cost-effective single chip fast ethernet mac controller with a general processor interface, a 10/100m phy and 16k byte sram. it is designed with low power and high performance process that support 3.3v with 5v tolerance. the dm9010 also provides a mii interface to connect hpna device or other transceivers that support mii interface. the dm9010 supports 8-bit, 16-bit and 32-bit up interfaces to inte rnal memory accesses for different processors. the phy of the dm9010 can interface to the utp3, 4, 5 in 10base-t and utp5 in 100base-tx. it is fully compliant with the ieee 802.3u spec. its auto-negotiation function will automatically configure the dm9010 to take the maximum advantage of its abilities. the dm9010 also supports ieee 802.3x full- duplex flow control. this programming of the dm9010 is very simple, so user can port the software drivers to any system easily. 2. block diagram led tx+/- rx+/- autonegotiation rx machine tx machine mac mii - / phyceiver processer interface - eeprom interface 100 basetx transceiver external mii interface memory management internal sram & control status registers 100 base - tx pcs 10 base t tx rx auto mdix & mii management control mii register dm9010 single chip ethernet controller with general processor interface preliminary 8 version: dm9010-ds-p03 apr. 28, 2005 3. features ? 100-pin lqfp. ? supports processor interface: byte/word/dword of i/o command to internal memory data operation ? integrated 10/100m transceiver with auto-mdix ? supports mii and reverses mii interface ? supports back pressure mode for half-duplex mode flow control ? ieee802.3x flow control for full-duplex mode ? supports wakeup frame, link status change and magic packet events for remote wake up ? integrated 16k byte sram ? build in 3.3v to 2.5v regulator ? supports early transmit ? supports ip/tcp/udp checksum generation and checking ? supports automatically load vendor id and product id from eeprom ? supports 7 or 23 gpio pins ? optional eeprom configuration ? very low power consumption mode: y power reduced mode (cable detection) y power down mode y selectable tx drivers for 1:1 or 1.25:1 transformers for additional power reduction. y 1: 1 transformers only when auto mdix enable . ? compatible with 3.3v and 5.0v tolerant i/o dm9010 single chip ethernet controller with general processor interface preliminary 9 version: dm9010-ds-p03 apr. 28, 2005 4. pin configuration 4.1 pin configuration i: with mii interface 11 dm9010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 32 31 30 29 28 27 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 76 77 78 79 80 81 82 83 84 gp5 gp4 vdd vdd gp3 gp2 gp1 gp0 eeck eecs eedo eedi gnd lkled fdled spled 20mck gnd mdc mdio txe txd3 txd2 txd1 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 rxvdd25 txd0 txc test5 rxc rxer rxdv col gnd rxd3 crs rxd2 rxd1 link_i nc tx- rxd0 txvdd25 tx+ rxgnd rx- rx+ txgnd rxvdd25 bgres gnd gp6 link_o wake pwrst# gnd sd15 sd14 sd13 sd12 io16 sd11 sd10 sd9 sd8 vdd cmd sa4 sa5 sa6 sa7 sa8 sa9 gnd int ior# iow# aen# iowait# vdd sd1 sd2 sd0 sd3 sd4 sd5 sd6 sd7 rst gnd test1 test2 test3 test4 vdd x2 x1 gnd sd bggnd 26 36 56 vdd dm9010 single chip ethernet controller with general processor interface preliminary 10 version: dm9010-ds-p03 apr. 28, 2005 4.2 pin configuration ii: with 32-bit data bus 11 dm9010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 32 31 30 29 28 27 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 76 77 78 79 80 81 82 83 84 gp5 gp4 vdd vdd gp3 gp2 gp1 gp0 eeck eecs eedo eedi gnd lkled fdled spled 20mck gnd io32 sd16 nc sd17 sd18 sd19 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 rxvdd25 sd20 sd21 test5 sd22 sd23 sd24 sd25 gnd sd27 sd26 sd28 sd29 sd31 nc tx- sd30 txvdd25 tx+ rxgnd rx- rx+ txgnd rxvdd25 bgres gnd gp6 link_o wake pwrst# gnd sd15 sd14 sd13 sd12 io16 sd11 sd10 sd9 sd8 vdd cmd sa4 sa5 sa6 sa7 sa8 sa9 gnd int ior# iow# aen# iowait# vdd sd1 sd2 sd0 sd3 sd4 sd5 sd6 sd7 rst gnd test1 test2 test3 test4 vdd x2 x1 gnd sd bggnd 26 36 56 vdd dm9010 single chip ethernet controller with general processor interface preliminary 11 version: dm9010-ds-p03 apr. 28, 2005 5. pin description i= input, o=output, i/o= input/output, o/d= open drain, p= power, li= reset latch input, #= asserted low, pd=internal pull-low about 60k ohm, pu=internal pull-high 5.1 mii interface pin no. pin name i/o description 37 link_i i,pd external mii device link status 41,40,39, 38 rxd [3:0] i,pd external mii receive data 4-bit nibble data input (synchronous to rxclk) when in 10/100 mbps. mii mode 43 crs i/o,pd external mii carrier sense active high to indicate the pressure of ca rrier, due to receive or transmit activities in 10 base-t or 100 base-tx mode. this pin is output in reverse mii interface. 44 col i/o,pd external mii collision detect. this pin is output in reverse mii interface. 45 rx_dv i,pd external mii receive data valid 46 rx_er i,pd external mii receive error 47 rx_clk i,pd external mii receive clock 49 tx_clk i/o,pd external mii transmit clock. this pin in output in mii interface. 53,52,51, 50 txd [3:0] o,pd external mii transmit data 4-bit nibble data outputs (synchronous to the tx_clk) when in 10/100mbps nibble mode txd [2:0] is also used as the strap pins of io base address. io base = (strap pin value of txd [2:0]) * 10h + 300h 54 tx_ en o,pd external mii transmit enable 56 mdio i/o,pd mii serial management data 57 mdc o,pd mii serial management data clock this pin is also used as the strap pin of the polarity of the int pin when the mdc pin is pulled high, the int pin is low active; otherwise the int pin is high active dm9010 single chip ethernet controller with general processor interface preliminary 12 version: dm9010-ds-p03 apr. 28, 2005 5.2 processor interface 1 ior# i,pd processor read command this pin is low active at default; its po larity can be modified by eeprom setting. see the eeprom content description for detail 2 iow# i,pd processor write command this pin is low active at default; its po larity can be modified by eeprom setting. see the eeprom content description for detail 3 aen i,pd address enable a low active signal used to select the dm9010. 4 iowait o,pd processor command ready when a command is issued before last command is completed, the iowait will be pulled low to indicate the current command is waited the polarity and output type can be updated by eeprom. the default is open-drain output and low active. 14 rst i,pd hardware reset command, active high to reset the dm9010 6,7,8,9,10, 11,12,13, 89,88,87, 86,85,84, 83,82 sd0~15 i/o,pd processor data bus bit 0~15 93,94,95, 96,97,98 sa4~9 i,pd address bus 4~9 these pins are used to select the dm9010. when sa9 and sa8 are in high states, and sa7 and aen are in low states, and sa6~4 are matched with strap pins txd2~0, the dm9010 is selected. 92 cmd i,pd command type when high, the access of this command cycle is data port when low, the access of this command cycle is index port 91 io16 o word command indication when the access of internal memory is word or dword width, this pin will be asserted this pin is low active at default; its polarity can be modified by eeprom setting. see the eeprom content description for detail 100 int o,pd interrupt request this pin is high active at default, its polarity can be modified by eeprom setting or strap pin mdc. see the eeprom content description for detail 56,53,52, 51,50,49, 47,46,45, 44,43,41, 40,39,38 37 sd16~31 (in double word mode) i/o,pd processor data bus bit 16~31 these pins are used as data bus bits 16~31 when the dm9010 is set to double word mode (the straps pin eedo is pulled high and wake is not pull-high) 57 io32 (in double word mode) o,pd double word command indication this pins is used as the double word command indication when the dm9010 is set to double data word mode, and this pin will be asserted when the access of internal memory is double word width this pin is low active at default; its polarity can be modified by eeprom setting. see the eeprom content description for detail when the io32 pin is pulled high, the int pin is low active; otherwise the int pin is high active dm9010 single chip ethernet controller with general processor interface preliminary 13 version: dm9010-ds-p03 apr. 28, 2005 5.3 eeprom interface 64 eedi i data from eeprom 65 eedo o,pd data to eeprom this pin is also used as a strap pin. it combines with strap pin wol, and it can set the data width of the internal memory access the decoder table is the following, where the logic 1 means the strap pin is pulled high wake eedo data width 0 0 16-bit 0 1 32-bit 1 0 8-bit 1 1 reserved 66 eeck o,pd clock to eeprom 67 eecs o,pd chip select to eeprom this pin is also used as a strap pin to define the led modes. when it is pulled high, the led mode is mode 1; otherwise it is mode 0 note: the pins eecs,eeck and eedo are all have a pulled down resistor about 60k ohm internally 5.4 clock interface 21 x2_25m o crystal 25mhz out 22 x1_25m i crystal 25mhz in 59 clk20mo i/o,pd 20mhz clock output it is used as the clock signal for the external mii device?s clock is 20mhz this pin has a pulled down resistor about 60k ohm internally. when pin test5 state is high, this pin act as the system clock. 5.5 led interface 60 spled o speed led its low output indicates that the internal phy is operated in 100m/s, or it is floating for the 10m mode of the internal phy 61 fdled o full-duplex led in led mode 1, its low output indicates that the internal phy is operated in full-duplex mode, or it is float ing for the half-duplex mode of the internal phy in led mode 0, its low output indicates that the internal phy is operated in 10m mode, or it is floating for the 100m mode of the internal phy 62 lkled o link / active led in led mode 1, it is the combined led of link and carrier sense signal of the internal phy in led mode 0, it is the led of the carrier sense signal of the internal phy only dm9010 single chip ethernet controller with general processor interface preliminary 14 version: dm9010-ds-p03 apr. 28, 2005 5.6 10/100 phy/fiber 24 sd i fiber-optic signal detect pecl signal, which indicates whether or not the fiber-optic receive pair is receiving valid levels 25 bggnd p bandgap ground 26 bgres i/o bandgap pin 27,28 rxvdd25 p internal regulator 2.5v output for tp rx 29 rxi+ i/o tp rx input 30 rxi- i/o tp rx input 31 rxgnd p rx ground 32 txgnd p tx ground 33 txo+ i/o tp tx output 34 txo- i/o tp tx output 35 txvdd25 p internal regulator 2.5v output for tp tx 5.7 miscellaneous 16,17,18, 19 test1~test4 i operation mode test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application 48 test5 i,pd internal system clock source 0: use internal 50mhz clock *(suggestion) 1: use clk20mo pin 68,69,70, 71, 74,75,77 gp0~6 i/o,pd general i/o ports registers gpcr and gpr can program these pins the gpio0 is an output mode, and output data high at default is to power down internal phy and other external mii device gp1~3 defaults are input ports, gp 0,4~6 force to output ports. 78 link_o o,pd cable link status output. active high this pin is also used as a strap pin to define whether the mii interface is a reversed mii interface (pulled high) or a normal mii interface (not pulled high). this pin has a pulled down resistor about 60k ohm internally. 79 wake o,pd issue a wake up signal when wake up event happens this pin has a pulled down resistor about 60k ohm internally. 80 pw_rst# i power on reset active low signal to initiate the dm9010 the dm9010 is ready after 5us when this pin deasserted 36 nc nc nc 5.8 power pins 5,20,55, 72,90,73 dvdd p digital vdd 15,23,42, 58,63,81, 99,76 gnd p digital gnd dm9010 single chip ethernet controller with general processor interface preliminary 15 version: dm9010-ds-p03 apr. 28, 2005 5.9 strap pins table 1: pull-high 1k~10k, 0: floating. pin no. pin name description 57 mdc polarity of int 1: int pin low active; 0: int pin high active 65 79 eedo wake data bus width wake eedo data width 0 0 16-bit 0 1 32-bit 1 0 8-bit 1 1 reserved 67 eecs led mode when it is pulled high, the led mode is mode 1; otherwise it is mode 0 52,51, 50 txd[2:0] io base address. ( not available in 32-bit mode) io base = (strap pin value of txd [2:0]) * 10h + 300h 78 link_o reverse mii 1: reverse mii mode 0: normal mii mode 53 txd[3] external mii mode (not available in 32-bit mode) force to external mii mode , mapping to bit 5 of reg. 2eh and set register ncr bit7 ?1?, 54 txen disable to load eeprom after power on reset. 74 gpio4 phy power-up. 1: phy is power-up after power-on 0: phy is power-down after power-on 75 gpio5 output type of int 1: int pin is open-collect 0: int pin is force output 77 gpio6 auto mdix 0: auto-mdix turn on 1: auto-mdix turn off 6. vendor control and status register set the dm9010 implements several control and status registers, which can be accessed by the host. these csrs are byte aligned. all csrs are set to their default values by hardware or software reset unless they are specified register description offset default value after reset ncr network control register 00h 00h nsr network status register 01h 00h tcr tx control register 02h 00h tsr i tx status register i 03h 00h tsr ii tx status register ii 04h 00h rcr rx control register 05h 00h rsr rx status register 06h 00h rocr receive overflow counter register 07h 00h dm9010 single chip ethernet controller with general processor interface preliminary 16 version: dm9010-ds-p03 apr. 28, 2005 bptr back pressure threshold register 08h 37h fctr flow control threshold register 09h 38h fcr rx flow control register 0ah 00h epcr eeprom & phy control register 0bh 00h epar eeprom & phy address register 0ch 40h epdrl eeprom & phy low byte data register 0dh xxh epdrh eeprom & phy high byte data register 0eh xxh wcr wake up control register 0fh 00h par physical address register 10h-15h determined by eeprom mar multicast address register 16h-1dh xxh gpcr general purpose control register 1eh 01h gpr general purpose register 1fh xxh trpal tx sram read pointer address low byte 22h 00h trpah tx sram read pointer address high byte 23h 00h rwpal rx sram write pointer address low byte 24h 00h rwpah rx sram write pointer address high byte 25h 0ch vid vendor id 28h-29h 0a46h pid product id 2ah-2bh 9000h chipr chip revision 2ch 10h tcr2 tx control register 2 2dh 00h ocr operation control register 2eh 00h smcr special mode control register 2fh 00h etxcsr early transmit control/status register 30h 00h tcscr transmit check sum control register 31h 00h rcscsr receive check sum control status register 32h 00h epadr external phy address 33h 01h gpcr2 general purpose control register 2 34h 00h gpr2 general purpose register 2 35h 00h gpcr3 general purpose control register 3 36h 00h gpr3 general purpose register 3 37h 00h monir1 monitor register 1 40h xxh monir2 monitor register 2 41h xxh mrcmdx memory data pre-fetch read command without address increment register f0h xxh mrcmdx1 memory data read command with address increment register f1h xxh mrcmd memory data read command with address increment register f2h xxh mrrl memory data read_ address register low byte f4h 00h mrrh memory data read_ address register high byte f5h 00h mwcmdx memory data write command without address increment register f6h xxh mwcmd memory data write command with address increment register f8h xxh mwrl memory data write_ address register low byte fah 00h mwrh memory data write _ address register high byte fbh 00h txpll tx packet length low byte register fch xxh dm9010 single chip ethernet controller with general processor interface preliminary 17 version: dm9010-ds-p03 apr. 28, 2005 txplh tx packet length high byte register fdh xxh isr interrupt status register feh 00h imr interrupt mask register ffh 00h key to default in the register description that follows, the default column takes the form: dm9010 single chip ethernet controller with general processor interface preliminary 18 version: dm9010-ds-p03 apr. 28, 2005 1 rxov phs0,ro rx fifo overflow 0 reserved 0,ro reserved 6.3 tx control register (02h) bit name default description 7 reserved 0,ro reserved 6 tjdis phs0,rw transmit jabber disable when set, the transmit jabber timer (2048 bytes) is disabled. otherwise it is enable 5 excecm phs0,rw excessive collision mode control : 0:aborts this packet when excessive collision counts more than 15, 1: still tr ies to transmit this packet 4 pad_dis2 phs0,rw pad appends disable for packet index 2 3 crc_dis2 phs0,rw crc appends disable for packet index 2 2 pad_dis1 phs0,rw pad appends disable for packet index 1 1 crc_dis1 phs0,rw crc appends disable for packet index 1 0 txreq phs0,rw tx request. auto clears after sending completely 6.4 tx status register i ( 03h ) for packet index i bit name default description 7 tjto phs0,ro transmit jabber time out it is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 lc phs0,ro loss of carrier it is set to indicate the loss of carrier during the frame transmission. it is not valid in internal loopback mode 5 nc phs0,ro no carrier it is set to indicate that there is no carrier signal during the frame transmission. it is not valid in internal loopback mode 4 lc phs0,ro late collision it is set when a collision occurs after the collision window of 64 bytes 3 col phs0,ro collision packet it is set to indicate that the collision occurs during transmission 2 ec phs0,ro excessive collision it is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 reserved 0,ro reserved 6.5 tx status register ii ( 04h ) for packet index i i bit name default description 7 tjto phs0,ro transmit jabber time out it is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted 6 lc phs0,ro loss of carrier it is set to indicate the loss of carrier during the frame transmission. it is not valid in internal loopback mode 5 nc phs0,ro no carrier it is set to indicate that there is no carrier signal during the frame transmission. it is not valid in internal loopback mode dm9010 single chip ethernet controller with general processor interface preliminary 19 version: dm9010-ds-p03 apr. 28, 2005 4 lc phs0,ro late collision it is set when a collision occurs after the collision window of 64 bytes 3 col phs0,ro collision packet, collision occurs during transmission 2 ec phs0,ro excessive collision it is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0 reserved 0,ro reserved 6.6 rx control register ( 05h ) bit name default description 7 hashall phs0,rw filter all address in hash table 6 wtdis phs0,rw watchdog timer disable when set, the watchdog timer (2048 bytes) is disabled. otherwise it is enabled 5 dis_long phs0,rw discard long packet packet length is over 1522byte 4 dis_crc phs0,rw discard crc error packet 3 all phs0,rw pass all multicast 2 runt phs0,rw pass runt packet 1 prmsc phs0,rw promiscuous mode 0 rxen phs0,rw rx enable 6.7 rx status register ( 06h ) bit name default description 7 rf phs0,ro runt frame it is set to indicate that the size of the received frame is smaller than 64 bytes 6 mf phs0,ro multicast frame it is set to indicate that the received frame has a multicast address 5 lcs phs0,ro late collision seen it is set to indicate that a late collision is found during the frame reception 4 rwto phs0,ro receive watchdog time-out it is set to indicate that it receives more than 2048 bytes 3 ple phs0,ro physical layer error it is set to indicate that a physical layer error is found during the frame reception 2 ae phs0,ro alignment error it is set to indicate that the received frame ends with a non-byte boundary 1 ce phs0,ro crc error it is set to indicate that the rece ived frame ends with a crc error 0 foe phs0,ro fifo overflow error it is set to indicate that a fifo overflow error happens during the frame reception 6.8 receive overflow counter register ( 07h ) bit name default description 7 rxfu phs0,r/c receive overflow counter overflow this bit is set when the roc has an overflow condition 6:0 roc phs0,r/c receive overflow counter this is a statistic counter to indicate the received packet count upon fifo overflow dm9010 single chip ethernet controller with general processor interface preliminary 20 version: dm9010-ds-p03 apr. 28, 2005 6.9 back pressure threshold register (08h) bit name default description 7:4 bphw phs3, rw back pressure high water overflow threshold. mac will generate the jam pattern when rx sram free space is lower than this threshold value default is 3k-byte free space. please do not exceed sram size (1 unit=1k bytes) 3:0 jpt phs7, rw jam pattern time. default is 200us bit3 bit2 bit1 bit0 time 0 0 0 0 5us 0 0 0 1 10us 0 0 1 0 15us 0 0 1 1 25us 0 1 0 0 50us 0 1 0 1 100us 0 1 1 0 150us 0 1 1 1 200us 1 0 0 0 250us 1 0 0 1 300us 1 0 1 0 350us 1 0 1 1 400us 1 1 0 0 450us 1 1 0 1 500us 1 1 1 0 550us 1 1 1 1 600us 6.10 flow control threshold register ( 09h ) bit name default description 7:4 hwot phs3, rw rx fifo high water overflow threshold send a pause packet with pause_ time=ffffh when the rx ram free space is less than this value., if this value is zero, its means no free rx sram space. default is 3k-byte free space. please do not exceed sram size (1 unit=1k bytes) 3:0 lwot phs8, rw rx fifo low water overflow threshold send a pause packet with pause_time=0000 when rx sram free space is larger than this value. this pause packet is enabled after the high water pause packet is transmitted. default sram free space is 8k-byte. please do not exceed sram size (1 unit=1k bytes) 6.11 rx/tx flow control register ( 0ah ) bit name default description 7 txp0 hps0,rw tx pause packet auto clears after pause packet transmission completion. set to tx pause packet with time = 0000h 6 txpf hps0,rw tx pause packet auto clears after pause packet transmission completion. set to tx pause packet with time = ffffh 5 txpen hps0,rw force tx pause packet enable enables the pause packet for high/low water threshold control dm9010 single chip ethernet controller with general processor interface preliminary 21 version: dm9010-ds-p03 apr. 28, 2005 4 bkpa hps0,rw back pressure mode this mode is for half duplex mode only. it generates a jam pattern when any packet comes and rx sram is over bphw 3 bkpm hps0,rw back pressure mode this mode is for half duplex mode only. it generates a jam pattern when a packet?s da matches and rx sram is over bphw 2 rxps hps0,r/c rx pause packet status, latch and read clearly 1 rxpcs hps0,ro rx pause packet current status 0 flce hps0,rw flow control enable set to enable the flow control mode (i.e. to disable tx function) 6.12 eeprom & phy control register ( 0bh ) bit name default description 7:6 reserved 0,ro reserved 5 reep ph0,rw reload eeprom. driver needs to clear it up after the operation completes 4 wep ph0,rw write eeprom enable 3 epos ph0,rw eeprom or phy operation select when reset, select eeprom; when set, select phy 2 erprr ph0,rw eeprom read or phy register read command. driver needs to clear it up after the operation completes. 1 erprw ph0,rw eeprom write or phy register write command. driver needs to clear it up after the operation completes. 0 erre ph0,ro eeprom access status or phy access status when set, it indicates that the eeprom or phy access is in progress 6.13 eeprom & phy address register ( 0ch ) bit name default description 7:6 phy_adr ph01,rw phy address bit 1 and 0, the phy address bit [4:2] is force to 0. force to 01 if internal phy is selected 5:0 eroa ph0,rw eeprom word address or phy register address 6.14 eeprom & phy data register (ee_phy_l j 0dh ee_phy_h j 0eh) bit name default description 7:0 ee_phy_l ph0,rw eeprom or phy low byte data this data is made to write low byte of word address defined in reg. ch to eeprom or phy 7:0 ee_phy_h ph0,rw eeprom or phy high byte data this data is made to write high byte of word address defined in reg. ch to eeprom or phy 6.15 wake up control register ( 0fh ) bit name type description 7:6 reserved 0,ro reserved 5 linken p0,rw when set, it enables link status change wake up event this bit will not be affected after software reset 4 sampleen p0,rw when set, it enables sample frame wake up event dm9010 single chip ethernet controller with general processor interface preliminary 22 version: dm9010-ds-p03 apr. 28, 2005 this bit will not be affected after software reset 3 magicen p0,rw when set, it enables magic packet wake up event this bit will not be affected after software reset 2 linkst p0,ro when set, it indicates that link change and link status change event occurred this bit will not be affected after software reset 1 samplest p0,ro when set, it indicates that the sample frame is received and sample frame event occurred. this bit will not be affected after software reset 0 magicst p0,ro when set, indicates the magic packet is received and magic packet event occurred. this bit will not be affected after a software reset 6.16 physical address register ( 10h~15h ) bit name default description 7:0 pab5 e,rw physical address byte 5 (15h) 7:0 pab4 e,rw physical address byte 4 (14h) 7:0 pab3 e,rw physical address byte 3 (13h) 7:0 pab2 e,rw physical address byte 2 (12h) 7:0 pab1 e,rw physical address byte 1 (11h) 7:0 pab0 e,rw physical address byte 0 (10h) 6.17 multicast address register ( 16h~1dh ) bit name default description 7:0 mab7 x,rw multicast address byte 7 (1dh) 7:0 mab6 x,rw multicast address byte 6 (1ch) 7:0 mab5 x,rw multicast address byte 5 (1bh) 7:0 mab4 x,rw multicast address byte 4 (1ah) 7:0 mab3 x,rw multicast address byte 3 (19h) 7:0 mab2 x,rw multicast address byte 2 (18h) 7:0 mab1 x,rw multicast address byte 1 (17h) 7:0 mab0 x,rw multicast address byte 0 (16h) 6.18 general purpose control register ( 1eh ) bit name default description 7 reserved 0,ro reserved 6:4 gpc64 ph, 111,ro general purpose control 6~4 define the input/output direction of pins gpio6~4 respectively. these bits are all forced to ?1?s, so pins gpio6~4 are output only. 3:1 gpc31 ph, 000,rw general purpose control 3~1 define the input/output direction of pins gpio 3~1 respectively. when a bit is set 1, the direction of correspondent bit of general purpose register is output. other defaults are input 0 gpc0 ph1,ro general purpose control 0 this bit define the input/output direction of pin gpio0. these bits are forced to ?1?, so pin gpio0 is output only. pin gpio0 is forced to output for in ternal phyceiver power down function. 6.19 general purpose register ( 1fh ) bit name default description 7 reserved 0,ro reserved dm9010 single chip ethernet controller with general processor interface preliminary 23 version: dm9010-ds-p03 apr. 28, 2005 6:4 gepio6-4 ph0,rw general purpose data 6~4 these bits are reflect to pin gepio6~4 respectively. 3:1 gepio3-1 ph0,rw general purpose 3~1 when the correspondent bit of general purpose control register is 1, the value of the bit is reflected to pin gepio3-1 when the correspondent bit of general purpose control register is 0, the value of the bit to be read is reflected from correspondent pins of gepio3-1 the gepios are mapped to pins gepio3 to gepio1 respectively 0 gepio0 et1,rw general purpose 0 the value of the bit is the output to pin gepio0 this bit also defines the power down status of internal phyceiver. driver needs to clear this bit by writing ?0? when it wants internal phyceiver to be power up. this default value can be programmed by strap pin gpio4 or eeprom. please refer to the eeprom description 6.20 tx sram read pointer address register (22h~23h) bit name default description 7:0 trpah ps0,ro tx sram read pointer address high byte (23h) 7:0 trpal ps0.ro tx sram read pointer address low byte (22h) 6.21 rx sram write pointer address register (24h~25h) bit name default description 7:0 rwpah ps,0ch,ro rx sram write pointer address high byte (25h) 7:0 rwpal ps,04h.ro rx sram write pointer address low byte (24h) 6.22 vendor id register (28h~29h) bit name default description 7:0 vidh phe,0ah,ro vendor id high byte (29h) 7:0 vidl phe,46h.ro vendor id low byte (28h) 6.23 product id register (2ah~2bh) bit name default description 7:0 pidh phe,90h,ro product id high byte (2bh) 7:0 pidl phe,00h.ro product id low byte (2ah) 6.24 chip revision register (2ch) bit name default description 7:0 chipr 10h,ro chip revision 6.25 transmit control register 2 ( 2dh ) bit name default description 7 led ph0,rw led mode when set, the led pins act as led mode 1. when cleared, the led mode is depending on strap pin or eeprom setting. dm9010 single chip ethernet controller with general processor interface preliminary 24 version: dm9010-ds-p03 apr. 28, 2005 6 rlcp ph0,rw retry late_collision packet re-transmit the packet with late-collision 5 dtu ph0,rw disable tx underrun retry disable to re-transmit the underruned packet 4 onepm ph0,rw one packet mode when set, only one packet transmit command can be issued before transmit completed. when cleared, at most two packet transmit command can be issued before transmit completed. 3~0 ifgs ph0,rw inter-frame gap setting 0xxx: 96-bit 1000: 64-bit 1001: 72-bit 1010:80-bit 1011:88-bit 1100:96-bit 1101:104-bit 1110: 112-bit 1111:120-bit 6.26 operation test control register ( 2eh ) bit name default description 7~6 scc ph0,rw system clock control set the internal system clock. 00: 50mhz 01: 20mhz 10: 100mhz 11:1khz in external mii mode, only internal system clock is always 50mhz. 5 extmii ph0,rw force to external mii mode 4 soe ph0,rw sram output-enable always on 3 scs ph0,rw sram chip-select always on 2~0 phyop ph0,rw phy operation mode 6.27 special mode control register ( 2fh ) bit name default description 7 sm_en hps0,rw special mode enable 6~3 reserved hps0,ro reserved 2 flc hps0,rw force late collision 1 fb1 hps0,rw force longest back-off time 0 fb0 hps0,rw force shortest back-off time 6.28 early transmit control/status register ( 30h ) bit name default description 7 ete hps0, rw early transmit enable enable bits[1:0] 6 ets2 hps0,ro early transmit status ii (underrun) 5 ets1 hps0,ro early transmit status i (underrun) 4~2 reserved 000,ro reserved dm9010 single chip ethernet controller with general processor interface preliminary 25 version: dm9010-ds-p03 apr. 28, 2005 1~0 ett hps0,rw early transmit threshold start transmit when data write to tx fifo reach the byte-count threshold bit-1 bit-0 threshold ----- ---- ------------- 0 0 : 12.5% 0 1 : 25% 1 0 : 50% 1 1 : 75% 6.29 transmit check sum control register ( 31h ) bit name default description 7~3 reserved 0,ro reserved 2 udpcse hps0,rw udp checksum generation enable 1 tcpcse hps0,rw tcp checksum generation enable 0 ipcse hps0,rw ip checksum generation enable 6.30 receive check sum control status register ( 32h ) bit name default description 7 udps hps0,ro udp checksum status 0: checksum ok, if udp packet 6 tcps hps0,ro tcp checksum status 0: checksum ok, if tcp packet 5 ips hps0,ro ip checksum status 0: checksum ok, if ip packet 4 udpp hps0,ro udp packet 3 tcpp hps0,ro tcp packet 2 ipp hps0,ro ip packet 1 rcsen hps0,r w receive checksum checking enable when set, the checksum status will store in packet first byte of status header. 0 dcse hps0,r w discard checksum error packet when set, if ip/tcp/udp checksum field is error, this packet will be discarded. 6.31 external phyceiver address register ( 33h ) bit name default description 7 adr_en hps0,r w external phy address enabled when set in external mii mode, the external phyceiver address is defined at bit 4~0. 6~5 reserved hps0,ro reserved 4~0 ephyadr hps01,r w external phy address bit 4~0 the phy address in external mii mode. 6.32 general purpose control register 2 ( 34h ) bit name default description dm9010 single chip ethernet controller with general processor interface preliminary 26 version: dm9010-ds-p03 apr. 28, 2005 7~0 gpc2 hp0,rw general purpose control 2 define the input/output direction of pins sd23~16, which are used as general purpose pins when none 32-bit mode and external mii mode, respectively. 6.33 general purpose register 2 ( 35h ) bit name default description 7~0 gpd2 hp0,rw general purpose register 2 data when the correspondent bit of general purpose control register 2 is set, the value of the bit is reflected to pin sd23~16 when the correspondent bit of general purpose control register 2 is 0, the value of the bit to be read is reflected from correspondent pins sd23~16 6.34 general purpose control register 3 ( 36h ) bit name default description 7~0 gpc3 hp0,rw general purpose control 3 define the input/output direction of pins sd31~24, which are used as general purpose pins when none 32-bit mode and external mii mode, respectively. 6.35 general purpose register 3 ( 37h ) bit name default description 7~0 gpd3 hp0,rw general purpose register 3 data when the correspondent bit of general purpose control register 3 is set, the value of the bit is reflected to pin sd31~24 when the correspondent bit of general purpose control register 3 is 0, the value of the bit to be read is reflected from correspondent pins sd31~24 6.36 monitor register 1 ( 40h ) bit name default description 7 bwidth t0,ro 8-bit data strap latch status 6 dwidth t0,ro 32-bit data strap latch status 5 intoc et0,ro int open-collect pin status 4 intp et0,ro int polarity pin status 3 io16oc e0,ro io16/32 open-collect pin status 2 io16p e0,ro io16/32 polarity pin status 1 iledm et0,ro led mode status 0 mdix et0,ro mdix strap pin status 6.37 monitor register 2 ( 41h ) bit name default description 7~4 reserved 0,ro reserved 3 noeep t0,ro no load eeprom strap pin status 2 extmii t0,ro external mii strap pin status 1 phyup t0,ro phy power-up strap pin status 0 rmii t0,ro reverse mii strap pin status dm9010 single chip ethernet controller with general processor interface preliminary 27 version: dm9010-ds-p03 apr. 28, 2005 6.38 memory data pre-fetch read command without address increment register (f0h) bit name default description 7:0 mrcmdx x,ro read data from rx sram. after the read of this command, the read pointer of internal sram is unchanged. and the dm9010 starts to pre-fetch the sram data to internal data buffers. 6.39 memory data read command without address increment register (f1h) bit name default description 7:0 mrcmdx1 x,ro read data from rx sram. after the read of this command, the read pointer of internal sram is unchanged. 6.40 memory data read command with address increment register (f2h) bit name default description 7:0 mrcmd x,ro read data from rx sram. after the read of this command, the read pointer is increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit respectively) 6.41 memory data read_address register (f4h~f5h) bit name default description 7:0 mdrah phs0,rw memory data read_ address high byte. it will be set to 0ch, when imr bit7 =1 7:0 mdral phs0,rw memory data read_ address low byte 6.42 memory data write command without address increment register (f6h) bit name default description 7:0 mwcmdx x,wo write data to tx sram. after the write of this command, the write pointer is unchanged 6.43 memory data write command with address increment register (f8h) bit name default description 7:0 mwcmd x,wo write data to tx sram after the write of this command, the write pointer is increased by 1,2, or 4, depends on the operator mode. (8-bit, 16-bit,32-bit respectively) 6.44 memory data write_address register (fah~fbh) bit name default description 7:0 mdrah phs0,rw memory data write_ address high byte 7:0 mdral phs0,rw memory data write_ address low byte 6.45 tx packet length register (fch~fdh) bit name default description dm9010 single chip ethernet controller with general processor interface preliminary 28 version: dm9010-ds-p03 apr. 28, 2005 7:0 txplh phs0,rw tx packet length high byte 7:0 txpll phs0,rw tx packet length low byte 6.46 interrupt status register (feh) bit name default description 7:6 iomode t0, ro bit 7 bit 6 0 0 16-bit mode 0 1 32-bit mode 1 0 8-bit mode 1 1 reserved 5 lnkchg phs0,rw/c1 link status change 4 udrun phs0,rw/c1 transmit underrun 3 roo phs0,rw/c1 receive overflow counter overflow 2 ros phs0,rw/c1 receive overflow 1 pt phs0,rw/c1 packet transmitted 0 pr phs0,rw/c1 packet received 6.47 interrupt mask register (ffh) bit name default description 7 par hps0,rw enable the sram read/write pointer to automatically return to the start address when pointer addresses are over the sram size. driver needs to set. when driver sets this bit, reg_f5 will set to 0ch automatically 6 reserved ro reserved 5 lnkchgi phs0,rw enable link status change interrupt 4 udruni phs0,rw enable transmit underrun interrupt 3 rooi phs0,rw enable receive overflow counter overflow interrupt 2 roi phs0,rw enable receive overflow interrupt 1 pti phs0,rw enable packet transmitted interrupt 0 pri phs0,rw enable packet received interrupt dm9010 single chip ethernet controller with general processor interface preliminary 29 version: dm9010-ds-p03 apr. 28, 2005 7. eeprom format name word offset description mac address 0 0~5 6 byte ethernet address auto load control 3 6-7 bit 1:0=01: update vendor id and product id bit 3:2=01: accept setting of word6 [8:0] bit 5:4=01: accept setting of word6 [11:9] bit 7:6=01: accept setting of word7 [3:0] bit 11:10=01: accept setting of word7 [7] bit 13:12=01: accept setting of word7 [8] bit 15:14=01: accept setting of word7 [14] vendor id 4 8-9 2 byte vendor id (default: 0a46h) product id 5 10-11 2 byte product id (default: 9000h) pin control 6 12-13 when word 3 bit [3:2]=01, these bits can control the ior#, iow# and int pins polarity. bit0: reserved bit1: ior# pin is active low when set (default: active low) bit2: iow# pin is active low when set (default: active low) bit3: int pin is active low when set (default: active high) bit4: int pin s open-collected (default: force output) bit 8:5: reserved when word 3 bit [5:4]=01, the i/o base can be re-configured. bit11:09: i/o base (default: 300h) 000 : 300h 001 : 310h 010 : 320h 011 : 330h 100 : 340h 101 : 350h 110 : 360h 111 : 370h bit15:12: reserved wake-up mode control 7 14-15 bit0: the wake pin is active low when set (default: active high) bit1: the wake pin is in pulse mode when set (default: level mode) bit2: magic wakeup event is enabled when set. (default: disable)) bit3: link_change wakeup event is enabled when set (default: disable) bit6:4: reserved bit7: led mode 1 (default: 0) bit8: internal phy is enabled after power-on (default: disable) bit13:9: reserved bit14: 1: auto-mdix on, 0: auto-mdix off(default on) bit15: reserved reserved 8 16-17 reserved 9 18-19 reserved 10 20-21 reserved 11 22-23 dm9010 single chip ethernet controller with general processor interface preliminary 30 version: dm9010-ds-p03 apr. 28, 2005 8. mii register description add name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset loop back speed select auto-n enable power down isolate restart auto-n full duplex coll. test reserved 00 contr ol 0 0 1 1 0 0 0 1 0 000_0000 t4 cap. tx fdx cap. tx hdx cap. 10 fdx cap. 10 hdx cap. reserved pream. supr. auto-n compl. remote fault auto-n cap. link status jabber detect extd cap. 01 status 0 1 1 1 1 0000 1 0 0 1 0 0 1 02 phyid1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 phyid2 1 0 1 1 1 0 model no. version no. 03 01010 0000 04 auto-neg. advertise next page flp rcv ack remote fault reserved fc adv t4 adv tx fdx adv tx hdx adv 10 fdx adv 10 hdx adv advertised protocol selector field 05 link part. ability lp next page lp ack lp rf reserved lp fc lp t4 lp tx fdx lp tx hdx lp 10 fdx lp 10 hdx link partner protocol selector field 06 auto-neg. expansio n reserved pardet fault lp next pg able next pg able new pg rcv lp auton cap. 16 specifie d config. bp 4b5b bp scr bp align bp_adp ok reserve dr tx reserve d reserve d force 100lnk reserve d reserve d rpdctr -en reset st. mch pream. supr. sleep mode remote loopout 17 specifie d conf/stat 100 fdx 100 hdx 10 fdx 10 hdx reserve d reverse d reverse d phy addr [4:0] auto-n. monitor bit [3:0] 18 10t conf/stat rsvd lp enable hbe enable sque enable jab enable reserve d reserved polarity reverse 19 pwdor reserved pd10dr v pd100l pdchip pdcrm pdaeq pddrv pdecli pdeclo pd10 20 specified config tstse1 tstse2 force_ txsd force_ fef reserved mdix_c ntl autoneg _dlpbk mdix_fix value mdix_do wn monsel1 monsel0 reserve d pd_valu e key to default in the register description that follows, the default column takes the form: dm9010 single chip ethernet controller with general processor interface preliminary 31 version: dm9010-ds-p03 apr. 28, 2005 8.1 basic mode control register (bmcr) - 00 bit bit name default description 0.15 reset 0, rw/sc reset 1=software reset 0=normal operation this bit sets the status and controls the phy registers to their default states. this bit, which is self-clearing, will keep returning a value of one until the reset process is completed 0.14 loopback 0, rw loopback loop-back control register 1 = loop-back enabled 0 = normal operation when in 100mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the mii receive outputs 0.13 speed selection 1, rw speed select 1 = 100mbps 0 = 10mbps link speed may be selected either by this bit or by auto-negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 0.12 auto-negotiatio n enable 1, rw auto-negotiation enable 1 = auto-negotiation is enable d, bit 8 and 13 will be in auto-negotiation status 0.11 power down 0, rw power down while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii 1=power down 0=normal operation 0.10 isolate 0,rw isolate force to 0 in application. 0.9 restart auto-negotiatio n 0,rw/sc restart auto-negotiation 1 = restart auto-negotiation. re -initiates the auto-negotiation process. when auto-n egotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the dm9010. the operation of the auto-neg otiation process will not be dm9010 single chip ethernet controller with general processor interface preliminary 32 version: dm9010-ds-p03 apr. 28, 2005 affected by the management entity that clears this bit 0 = normal operation 0.8 duplex mode 1,rw duplex mode 1 = full duplex operation. duplex selection is allowed when auto-negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = normal operation 0.7 collision test 0,rw collision test 1 = collision test enabled. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en in internal mii interface. 0 = normal operation 0.6-0.0 reserved 0,ro reserved read as 0, ignore on write 8.2 basic mode status register (bmsr) - 01 bit bit name default description 1.15 100base-t4 0,ro/p 100base-t4 capable 1 = dm9010 is able to perform in 100base-t4 mode 0 = dm9010 is not able to perform in 100base-t4 mode 1.14 100base-tx full-duplex 1,ro/p 100base-tx full duplex capable 1 = dm9010 is able to perform 100base-tx in full duplex mode 0 = dm9010 is not able to perform 100base-tx in full duplex mode 1.13 100base-tx half-duplex 1,ro/p 100base-tx half duplex capable 1 = dm9010 is able to perform 100base-tx in half duplex mode 0 = dm9010 is not able to perform 100base-tx in half duplex mode 1.12 10base-t full-duplex 1,ro/p 10base-t full duplex capable 1 = dm9010 is able to perform 10base-t in full duplex mode 0 = dm9010 is not able to perf orm 10base-tx in full duplex mode 1.11 10base-t half-duplex 1,ro/p 10base-t half duplex capable 1 = dm9010 is able to perform 10base-t in half duplex mode 0 = dm9010 is not able to perform 10base-t in half duplex mode 1.10-1.7 reserved 0,ro reserved read as 0, ignore on write dm9010 single chip ethernet controller with general processor interface preliminary 33 version: dm9010-ds-p03 apr. 28, 2005 1.6 mf preamble suppression 1,ro mii frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed 1.5 auto-negotiatio n complete 0,ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 1.4 remote fault 0, ro/lh remote fault 1 = remote fault condition detect ed (cleared on read or by a chip reset). fault criteria and detection method is dm9010 implementation specific. this bit will set after the rf bit in the anlpar (bit 13, register address 05) is set 0 = no remote fault condition detected 1.3 auto-negotiatio n ability 1,ro/p auto conf iguration ability 1 = dm9010 is able to perform auto-negotiation 0 = dm9010 is not able to perform auto-negotiation 1.2 link status 0,ro/ll link status 1 = valid link is established (for either 10mbps or 100mbps operation) 0 = link is not established the link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface 1.1 jabber detect 0, ro/lh jabber detect 1 = jabber condition detected 0 = no jabber this bit is implemented with a latching function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a dm9010 reset. this bit works only in 10mbps mode 1.0 extended capability 1,ro/p extended capability 1 = extended register capable 0 = basic register capable only dm9010 single chip ethernet controller with general processor interface preliminary 34 version: dm9010-ds-p03 apr. 28, 2005 8.3 phy id identifier register #1 (phyid1) - 02 the phy identifier registers #1 and #2 work together in a single identifier of the dm9010. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semiconductor's ieee assigned oui is 00606e. bit bit name default description 2.15-2.0 oui_msb <0181h> oui most significant bits this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the most significant two b its of the oui are ignored (the ieee standard refers to these as bit 1 and 2) 8.4 phy id identifier register #2 (phyid2) - 03 bit bit name default description 3.15-3.1 0 oui_lsb <101110>, ro/p oui least significant bits bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 3.9-3.4 vndr_mdl <001010>, ro/p vendor model number five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0 mdl_rev <0000>, ro/p model revision number five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) 8.5 auto-negotiation advertisement register (anar) - 04 this register contains the advertised abilities of this dm9010 device as they will be transmitted to its link partner during auto-negotiation. bit bit name default description 4.15 np 0,ro/p next page indication 0 = no next page available 1 = next page available the dm9010 has no next page, so this bit is permanently set to 0 4.14 ack 0,ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged the dm9010's auto-negotiation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 4.13 rf 0, rw remote fault dm9010 single chip ethernet controller with general processor interface preliminary 35 version: dm9010-ds-p03 apr. 28, 2005 1 = local device senses a fault condition 0 = no fault detected 4.12-4.1 1 reserved x, rw reserved write as 0, ignore on read 4.10 fcs 0, rw flow control support 1 = controller chip supports flow control ability 0 = controller chip doesn ? t support flow control ability 4.9 t4 0, ro/p 100base-t4 support 1 = 100base-t4 is supported by the local device 0 = 100base-t4 is not supported the dm9010 does not support 100base-t4 so this bit is permanently set to 0 4.8 tx_fdx 1, rw 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the local device 0 = 100base-tx full duplex is not supported 4.7 tx_hdx 1, rw 100base-tx support 1 = 100base-tx half duplex is supported by the local device 0 = 100base-tx half duplex is not supported 4.6 10_fdx 1, rw 10base-t full duplex support 1 = 10base-t full duplex is supported by the local device 0 = 10base-t full duplex is not supported 4.5 10_hdx 1, rw 10base-t support 1 = 10base-t half duplex is supported by the local device 0 = 10base-t half duplex is not supported 4.4-4.0 selector <00001>, rw protocol selection bits these bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports ieee 802.3 csma/cd 8.6 auto-negotiation link partner ability register (anlpar) ? 05 this register contains the advertised abiliti es of the link partner when received during auto-negotiation. bit bit name default description 5.15 np 0, ro next page indication 0 = link partner, no next page available 1 = link partner, next page available 5.14 ack 0, ro acknowledge 1 = link partner ability data reception acknowledged 0 = not acknowledged dm9010 single chip ethernet controller with general processor interface preliminary 36 version: dm9010-ds-p03 apr. 28, 2005 the dm9010's auto-negotiation state machine will automatically control this bi t from the incoming flp bursts. software should not attempt to write to this bit 5.13 rf 0, ro remote fault 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 5.12-5.1 1 reserved 0, ro reserved read as 0, ignore on write 5.10 fcs 0, ro flow control support 1 = controller chip supports flow control ability by link partner 0 = controller chip doesn ? t support flow control ability by link partner 5.9 t4 0, ro 100base-t4 support 1 = 100base-t4 is supported by the link partner 0 = 100base-t4 is not supported by the link partner 5.8 tx_fdx 0, ro 100base-tx full duplex support 1 = 100base-tx full duplex is supported by the link partner 0 = 100base-tx full duplex is not supported by the link partner 5.7 tx_hdx 0, ro 100base-tx support 1 = 100base-tx half duplex is supported by the link partner 0 = 100base-tx half duplex is not supported by the link partner 5.6 10_fdx 0, ro 10base-t full duplex support 1 = 10base-t full duplex is supported by the link partner 0 = 10base-t full duplex is not supported by the link partner 5.5 10_hdx 0, ro 10base-t support 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by the link partner 5.4-5.0 selector <00000>, ro protocol selection bits link partner ? s binary encoded protocol selector 8.7 auto-negotiation expansion register (aner)- 06 bit bit name default description 6.15-6.5 reserved 0, ro reserved read as 0, ignore on write 6.4 pdf 0, ro/lh local device parallel detection fault pdf = 1: a fault detected via parallel detection function. dm9010 single chip ethernet controller with general processor interface preliminary 37 version: dm9010-ds-p03 apr. 28, 2005 pdf = 0: no fault detected via parallel detection function 6.3 lp_np_abl e 0, ro link partner next page able lp_np_able = 1: link partner, next page available lp_np_able = 0: link partner, no next page 6.2 np_able 0,ro/p local device next page able np_able = 1: dm9010, next page available np_able = 0: dm9010, no next page dm9010 does not support this function, so this bit is always 0 6.1 page_rx 0, ro/lh new page received a new link code word page received. this bit will be automatically cleared when the register (register 6) is read by management 6.0 lp_an_abl e 0, ro link partner auto-negotiation able a ? 1 ? in this bit indicates that the link partner supports auto-negotiation 8.8 davicom specified configuration register (dscr) - 16 bit bit name default description 16.15 bp_4b5b 0,rw bypass 4b5b encoding and 5b4b decoding 1 = 4b5b encoder and 5b4b decoder function bypassed 0 = normal 4b5b and 5b4b operation 16.14 bp_scr 0, rw bypass scrambler/descrambler function 1 = scrambler and descrambler function bypassed 0 = normal scrambler and descrambler operation 16.13 bp_align 0, rw bypass symbol alignment function 1 = receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. transmit functions (symbol encoder and scrambler) bypassed 0 = normal operation 16.12 bp_adpok 0, rw bypass adpok force signal detector (sd) active. this register is for debug only, not release to customer 1=forced sd is ok, 0=normal operation 16.11 reserved rw reserved force to 0 in application 16.10 tx 1, rw 100base-tx mode control 1 = 100base-tx operation 16.9 reserved 0, ro reserved 16.8 reserved 0, rw reserved force to 0 in application. dm9010 single chip ethernet controller with general processor interface preliminary 38 version: dm9010-ds-p03 apr. 28, 2005 16.7 f_link_100 0, rw force good link in 100mbps 0 = normal 100mbps operation 1 = force 100mbps good link status this bit is useful for diagnostic purposes 16.6 reserved 0, rw reserved force to 0 in application. 16.5 reserved 0, rw reserved force to 0 in application. 16.4 rpdctr-en 1, rw reduced power down control enable this bit is used to enable automatic reduced power down 0 = disable automatic reduced power down 1 = enable automatic reduced power down 16.3 smrst 0, rw reset state machine when writes 1 to this bit, all state machines of phy will be reset. this bit is self-cle ar after reset is completed 16.2 mfpsc 1, rw mf preamble suppression control mii frame preamble suppression control bit 1 = mf preamble suppression bit on 0 = mf preamble suppression bit off 16.1 sleep 0, rw sleep mode writing a 1 to this bit will cause phy entering the sleep mode and power down all circuit except oscillator and clock generator circuit. when waking up from sleep mode (write this bit to 0), the configura tion will go back to the state before sleep; but the state machine will be reset 16.0 rlout 0, rw remote loopout control when this bit is set to 1, the re ceived data will loop out to the transmit channel. this is usef ul for bit error rate testing 8.9 davicom specified configuration and status register (dscsr) - 17 bit bit name default description 17.15 100fdx 1, ro 100m full duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 17.14 100hdx 1, ro 100m half duplex operation mode dm9010 single chip ethernet controller with general processor interface preliminary 39 version: dm9010-ds-p03 apr. 28, 2005 after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 100m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 17.13 10fdx 1, ro 10m full duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m full duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 17.12 10hdx 1, ro 10m half duplex operation mode after auto-negotiation is completed, results will be written to this bit. if this bit is 1, it means the operation 1 mode is a 10m half duplex mode. the software can read bit [15:12] to see which mode is selected after auto-negotiation. this bit is invalid when it is not in the auto-negotiation mode 17.11-17 .9 reserved 0, ro reserved read as 0, ignore on write 17.8-17. 4 phyadr [4:0] 1, rw phy address bit 4:0 the first phy address bit transmitted or received is the msb of the address (bit 4). a station manageme nt entity connected to multiple phy entities must know the appropriate address of each phy 17.3-17. 0 anmb[3: 0] 0, ro auto-negotiation monitor bits these bits are for debug only. the auto-negotiation status will be written to these bits. b3 b2 b1 b0 0 0 0 0 in idle state 0 0 0 1 ability match 0 0 1 0 acknowledge match 0 0 1 1 acknowledge match fail 0 1 0 0 consistency match 0 1 0 1 consistency match fail 0 1 1 0 parallel detects signal_link_ready 0 1 1 1 parallel detects signal_link_ready fail 8.10 10base-t configuration/status (10btcsr) - 18 bit bit name default description 18.15 reserved 0, ro reserved read as 0, ignore on write dm9010 single chip ethernet controller with general processor interface preliminary 40 version: dm9010-ds-p03 apr. 28, 2005 18.14 lp_en 1, rw link pulse enable 1 = transmission of link pulses enabled 0 = link pulses disabled, good link condition forced this bit is valid only in 10mbps operation 18.13 hbe 1,rw heartbeat enable 1 = heartbeat function enabled 0 = heartbeat function disabled when the dm9010 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) 18.12 squelch 1, rw squelch enable 1 = normal squelch 0 = low squelch 18.11 jaben 1, rw jabber enable enables or disables the jabber function when the dm9010 is in 10base-t full duplex or 10base-t transceiver loopback mode 1 = jabber function enabled 0 = jabber function disabled 18.10 reserved 0, rw reserved force to 0, in application. 18.9-18. 1 reserved 0, ro reserved read as 0, ignore on write 18.0 polr 0, ro polarity reversed when this bit is set to 1, it indicates that the 10mbps cable polarity is reversed. this bit is automatically set and cleared by 10base-t module 8.11 power down control register (pwdor) - 19 bit bit name default description 19.15-19. 9 reserved 0, ro reserved read as 0, ignore on write 19.8 pd10drv 0, rw vendor power down control test 19.7 pd100dl 0, rw vendor power down control test 19.6 pdchip 0, rw vendor power down control test 19.5 pdcom 0, rw vendor power down control test 19.4 pdaeq 0, rw vendor power down control test 19.3 pddrv 0, rw vendor power down control test 19.2 pdedi 0, rw vendor power down control test 19.1 pdedo 0, rw vendor power down control test 19.0 pd10 0, rw vendor power down control test * when selected, the power down value is control by register 20.0 dm9010 single chip ethernet controller with general processor interface preliminary 41 version: dm9010-ds-p03 apr. 28, 2005 8.12 (specified config) register ? 20 bit bit name default description 20.15 tstse1 0,rw vendor test select control 20.14 tstse2 0,rw vendor test select control 20.13 force_txs d 0,rw force signal detect 1: force sd signal ok in 100m 0: normal sd signal. 20.12 force_fef 0,rw vendor test select control 20.11-20 .8 reserved 0, ro reserved read as 0, ignore on write 20.7 mdix_cntl mdi/mdix, ro the polarity of mdi/mdix value 1: mdix mode 0: mdi mode 20.6 autoneg_dpb k 0,rw auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. 20.5 mdix_fix value 0, rw mdix_cntl force value: when mdix_down = 1, mdix_cntl value depend on the register value. 20.4 mdix_down 0,rw mdix down manual force mdi/mdix. 0: enable auto mdi/mdix 1: disable auto mdi/mdix, mdix_cntl value depend on 20.5 20.3 monsel1 0,rw vendor monitor select 20.2 monsel0 0,rw vendor monitor select 20.1 reserved 0,rw reserved force to 0, in application. 20.0 pd_value 0,rw power down control value decision the value of each field register 19. 1: power down 0: normal dm9010 single chip ethernet controller with general processor interface preliminary 42 version: dm9010-ds-p03 apr. 28, 2005 9. functional description 9.1 host interface the host interface is the isa bus compatible mode. there are eight io bases, which are 300h, 310h, 320h, 330h, 340h, 350h, 360h, and 370h. the io base is latched from strap pins or loaded from the eeprom. there are only two addressing ports through the access of the host interface. one port is the index port and the other is the data port. the index port is decoded by the pin cmd =0 and the data port by the pin cmd =1. the contents of the index port are the register address of the data port. before the access of any register, the address of the register must be saved in the index port. 9.2 direct memory access control the dm9010 provides dma capability to simplify the access of the internal memory. after the programming of the starting address of the internal memory and then issuing a dummy read/write command to load the current data to internal data buffer, the desired location of the internal memory can be accessed by the read/write command registers. the memory?s address will be increased with the size that equals to the current operation mode (i.e. the 8-bit, 16-bit or 32-bit mode) and the data of the next location will be loaded into internal data buffer automatically. it is noted that the data of the first access (the dummy read/write command) in a sequential burst should be ignored because that the data was the contents of the last read/write command. the internal memory size is 16k bytes. the first location of 3k bytes is used for the data buffer of the packet transmission. the other 13k bytes are used for the buffer of the receiving packets. so in the write memory operation, when the bit 7 of imr is set, the memory address increment w ill wrap to location 0 if the end of address (i.e. 3k) is reached. in a similar way, in the read memory operation, when the bit 7 of imr is set, the memory address increment will wrap to location 0x0c00 if the end of address (i.e. 16k) is reached. 9.3 packet transmission there are two packets, sequentially named as index i and index ii, can be stored in the tx sram at the same time. the index register 02h controls the insertion of crc and pads. their statuses are recorded at index registers 03h and 04h respectively. the start address of transmission is 00h and the current packet is index i after software or hardware reset. firstly write data to the tx sram using the dma port and then write the byte count to byte_ count register at index register 0fch and 0fdh. set the bit 1 of control register. the dm9010 starts to transmit the index i packet. before the transmission of the index i packet ends, the data of the next (index ii) packet can be moved to tx sram. after the index i packet ends the transmission, write the byte count data of the index ii to byte_count register and then set the bit 1 of control register to transmit the index ii packet. the following packets, named index i, ii, i, ii,?, use the same way to be transmitted. 9.4 packet reception the rx sram is a ring data structure. the start address of rx sram is 0c00h after software or hardware reset. each packet has a 4-byte header followed with the data of the reception packet which crc field is included. the format of the 4-byte header is 01h, status, byte_count low, and byte_count high. it is noted that the start address of each packet is in the proper address boundary which depends on the operation mode (the 8-bit, 16-bit or 32-bit mode). dm9010 single chip ethernet controller with general processor interface preliminary 43 version: dm9010-ds-p03 apr. 28, 2005 9.5 100base-tx operation the block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. the transmitter section contains the following functional blocks: - 4b5b encoder - scrambler - parallel to serial converter - nrz to nrzi converter - nrzi to mlt-3 - mlt-3 driver 9.5.1 4b5b encoder the 4b5b encoder converts 4-bit (4b) nibble data generated by the mac reconciliation layer into a 5-bit (5b) code group for transmission, see reference table 1. this conversion is required for control and packet data to be combined in code groups. the 4b5b encoder substitutes the first 8 bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmit. the 4b5b encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of the transmit enable signal from the mac reconciliation layer, the 4b5b encoder injects the t/r code-group pair (01101 00111) indicating the end of frame. after the t/r code-group pair, the 4b5b encoder continuously injects idles into the transmit data stream until transmit enable is asserted and the next transmit packet is detected. the dm9010 includes a bypass 4b5b conversion option within the 100base-tx transmitter for support of applications like 100 mbps repeaters which do not require 4b5b conversion. 9.5.2 scrambler the scrambler is required to control the radiated emissions (emi) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100base-tx operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scrambler, energy levels on the cable could peak beyond fcc limitations at frequencies related to the repeated 5b sequences, like the continuous transmission of idle symbols. the scrambler outp ut is combined with the nrz 5b data from the code-group encoder via an xor logic function. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.5.3 parallel to serial converter the parallel to serial conv erter receives parallel 5b scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi encoder block 9.5.4 nrz to nrzi encoder after the transmit data stream has been scrambled and serialized, the data must be nrzi encoded for compatibility with the tp-pmd standard, for 100base -tx transmission over category-5 unshielded twisted pair cable. 9.5.5 mlt-3 converter the mlt-3 conversion is accomplished by converting the data stream output, from the nrzi encoder into two binary data streams, with alternately phased logic one event. 9.5.6 mlt-3 driver the two binary data streams created at the mlt-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer ? s primary winding, resulting in a minimal current mlt-3 signal. refer to figure 4 for the block diagram of the mlt-3 converter. dm9010 single chip ethernet controller with general processor interface preliminary 44 version: dm9010-ds-p03 apr. 28, 2005 9.5.7 4b5b code group symbol meaning 4b code 3210 5b code 43210 0 data 0 0000 11110 1 data 1 0001 01001 2 data 2 0010 10100 3 data 3 0011 10101 4 data 4 0100 01010 5 data 5 0101 01011 6 data 6 0110 01110 7 data 7 0111 01111 8 data 8 1000 10010 9 data 9 1001 10011 a data a 1010 10110 b data b 1011 10111 c data c 1100 11010 d data d 1101 11011 e data e 1110 11100 f data f 1111 11101 i idle undefined 11111 j sfd (1) 0101 11000 k sfd (2) 0101 10001 t esd (1) undefined 01101 r esd (2) undefined 00111 h error undefined 00100 v invalid undefined 00000 v invalid undefined 00001 v invalid undefined 00010 v invalid undefined 00011 v invalid undefined 00101 v invalid undefined 00110 v invalid undefined 01000 v invalid undefined 01100 v invalid undefined 10000 v invalid undefined 11001 table 1 dm9010 single chip ethernet controller with general processor interface preliminary 45 version: dm9010-ds-p03 apr. 28, 2005 9.6 100base-tx receiver the 100base-tx receiver contains several function blocks that convert the scrambled 125mb/s serial data to synchronous 4-bit nibble data that is then provided to the mii. the receive section contains the following functional blocks: - signal detect - digital adaptive equalization - mlt-3 to binary decoder - clock recovery module - nrzi to nrz decoder - serial to parallel - descrambler - code group alignment - 4b5b decoder 9.6.1 signal detect the signal detects function meets the specifications mandated by the ansi xt12 tp-pmd 100base-tx standards for both voltage thresholds and timing parameters. 9.6.2 adaptive equalization when transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. in high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorter, less attenuating cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 9.6.3 mlt-3 to nrzi decoder the dm9010 decodes the mlt-3 information from the digital adaptive equalizer into nrzi data. the relationship between nrzi and mlt-3 data is shown in figure 4. 9.6.4 clock recovery module the clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the clock recovery module locks onto the data stream and extracts the 125 mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz decoder. 9.6.5 nrzi to nrz the transmit data stream is required to be nrzi encoded for compatibility wi th the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. this conversion process must be reversed on the receive end. the nrzi to nrz decoder, receives the nrzi data stream from the clock recovery module and converts it to a nrz data stream to be presented to the serial to parallel conversion block. 9.6.6 serial to parallel the serial to parallel converter receives a serial data stream from the nrzi to nrz converter. it converts the data stream to parallel data to be presented to the descrambler. 9.6.7 descrambler because of the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the descrambler receives scrambled parallel data streams from the serial to parallel converter, and it descrambles the data streams, and presents the data streams to the code group alignment block. dm9010 single chip ethernet controller with general processor interface preliminary 46 version: dm9010-ds-p03 apr. 28, 2005 9.6.8 code group alignment the code group alignment block receives un-aligned 5b data from the descrambler and converts it into 5b code group data. code group alignment occurs after the j/k is detected and subsequent data is aligned on a fixed boundary. 9.6.9 4b5b decoder the 4b5b decoder functions as a look-up table that translates incoming 5b code groups into 4b (nibble) data. when receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (j/k symbols). the j/k symbol pair is stripped and two nibbles of preamble pattern are substituted. the last two code groups are the end-of-frame delimiter (t/r symbols). the t/r symbol pair is also stripped from the nibble, presented to the reconciliation layer. 9.7 10base-t operation the 10base-t transceiver is ieee 802.3u compliant. when the dm9010 is operating in 10base-t mode, the coding scheme is manchester. data processed for transmit is presented to the mii interface in nibble format, converted to a serial bit stream, then the manchester encoded. when receiving, the bit stream, encoded by the manchester, is decoded and converted into nibble format to present to the mii interface. 9.8 collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. when a collision is detected, it will be reported by the col signal on the mii interface. collision detection is disabled in full duplex operation. 9.9 carrier sense carrier sense (crs) is asserted in half-duplex operation during transmission or reception of data. during full-duplex mode, crs is asserted only during receive operations. 9.10 auto-negotiation the objective of auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maximum advantage of their abilities. it is important to note that auto-negotiation does not test the characteristics of the linked segment. the auto-negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a segment to establish a link at the best common mode of operation. if more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. auto-negotiation also provides a parallel detection function for devices that do not support the auto-negotiation feature. during parallel detection there is no exchange of information of configuration. instead, the receive signal is examined. if it is discovered that the signal matches a technology, which the receiving device supports, a connection will be automatically established using that technology. this allows devices not to support auto-negotiation but support a common mode of operation to establish a link. dm9010 single chip ethernet controller with general processor interface preliminary 47 version: dm9010-ds-p03 apr. 28, 2005 9.11 power reduced mode the signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). the dm9010 automatically turns off the power and enters the power reduced mode, whether its operation mode is n-way or force mode. when enters the power reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption. if a valid signal is detected from the media, which might be n-ways fast link pules, 10base-t normal link pules, or 100base-tx mlt3 signals, the device will wake up and resume a normal operation mode. that can be writing zero to phy reg.16.4 to disable power reduced mode. 9.11.1 power down mode the phy reg.0.11 can be set high to enter the power down mode, which disables all transmit, receive functions and mii interface functions, except the mdc/mdio management interface. 9.11.2 reduced transmit power mode the additional transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its tx side and using a 8.5k ? resistor on bgres and agnd pins, and the txo+/txo- pulled high resistors should be changed from 50 ? to 78 ? . this configuration could be reduced about 20% transmit power. dm9010 single chip ethernet controller with general processor interface preliminary 48 version: dm9010-ds-p03 apr. 28, 2005 10. dc and ac electrical characteristics 10.1 absolute maximum ratings symbol parameter min. max. unit conditions d vdd supply voltage -0.3 3.6 v v in dc input voltage (vin) -0.5 5.5 v v out dc output voltage(vout) -0.3 3.6 v 10.1.1 operating conditions symbol parameter min. max. unit conditions d vdd supply voltage 3.135 3.465 v tc case temperature --- 85 c 100base-tx --- 87 ma 3.3v 10base-t tx (100% utilization) --- 92 ma 3.3v 10base-t idle --- 38 ma 3.3v auto-negotiation --- 56 ma 3.3v power reduced mode(withou t cable) --- 31 ma 3.3v p d (power dissipation) power down mode --- 21 ma 3.3v 10.2 dc electrical characteristics (vdd = 3.3v) symbol parameter min. typ. max. unit conditions inputs v il input low voltage - - 0.8 v v ih input high voltage 2.0 - - v i il input low leakage current -1 - - ua vin = 0.0v i ih input high leakage current - - 1 ua vin = 3.3v outputs v ol output low voltage - - 0.4 v iol = 4ma v oh output high voltage 2.4 - - v ioh = -4ma receiver v icm rx+/rx- common mode input voltage - 1.05 - v 100 ? termination across transmitter v td100 100tx+/- differential output voltage 1.9 2.0 2.1 v peak to peak v td10 10tx+/- differential output voltage 4.4 5 5.6 v peak to peak i td100 100tx+/- differential output current 19 20 21 ma absolute value i td10 10tx+/- differential output current 44 50 56 ma absolute value temperature tc case temperature 0 85 ta = 0 ~ 70 ta ambient temperature 0 70 tstg storage temperature -65 150 lt lead temperature - 235 10sec. max. dm9010 single chip ethernet controller with general processor interface preliminary 49 version: dm9010-ds-p03 apr. 28, 2005 10.3 ac electrical characteristics & timing waveforms 10.3.1 tp interface symbol parameter min. typ. max. unit conditions t tr/f 100tx+/- differential rise/fall time 3.0 - 5.0 ns t tm 100tx+/- differential rise/fall time mismatch 0 - 0.5 ns t tdc 100tx+/- differential output duty cycle distortion 0 - 0.5 ns t t/t 100tx+/- differential output peak-to-peak jitter 0 - 1.4 ns x ost 100tx+/- differential voltage overshoot 0 - 5 % 10.3.2 oscillator/crystal timing symbol parameter min. typ. max. unit conditions t ckc tckc 39.998 40 40.002 ns 50ppm t pwh osc pulse width high 16 20 24 ns t pwl osc pulse width low 16 20 24 ns 10.3.3 processor i/o read timing symbol parameter min. typ. max. unit t 1 system address(sa) valid to ior# valid 0 ns t 2 ior# width 10 ns t 3 ior# valid to system data(sd) valid 3 ns t 4 ior# invalid to system data(sd) bus invalid 3 ns t 5 ior# invalid to system address(sa) invalid 0 ns t 6 ior# invalid to next ior#/iow# valid when read dm9010 register 2 clk* t 6 ior# invalid to next ior#/iow# valid when read dm9010 memory with f0h register 4 clk* t 2 +t 6 ior# invalid to next ior#/iow# valid when read dm9010 memory with f2h register 1 clk* t 7 system address(sa) valid to io16,io32 valid 3 ns t 8 system address(sa) invalid to io16, io32 invalid 3 ns *note j (the default clk period is 20ns) dm9010 single chip ethernet controller with general processor interface preliminary 50 version: dm9010-ds-p03 apr. 28, 2005 1. the io16 is valid when the sd bus width is 16-bit or 32-bit, and the system address is data port (i.e. cmd is high) and the value of index port is memory data register index. ? ex. f0h, f2h, f6h or f8h ? 2. the io32 is valid when the sd bus width is 32-bit, the system address is data port (i.e. cmd is high) and the value of index port is memory data register index ? ex. f0h, f2h, f6h or f8h ? 10.3.4 processor i/o write timing symbol parameter min. typ. max. unit t 1 system aaddress(sa) valid to iow# valid 0 ns t 2 iow# width 10 ns t 3 system data(sd) setup time 3 ns t 4 system data (sd) hold time 3 ns t 5 iow# invalid to system address(sa) invalid 0 ns t 6 iow# invalid to next iow#/ior# valid when write dm9010 index port 1 clk* t 6 iow# invalid to next iow#/ior# valid when write dm9010 data port 2 clk* t 2 +t 6 iow# invalid to next iow#/ior# valid when write dm9010 memory 1 clk* t 7 system address(sa) valid to io16, io32 valid 3 ns t 8 system address(sa) invalid to io16, io32 invalid 3 ns note j (the default clk period is 20ns) 1. the io16 is valid when the sd bus width is 16-bit or 32-bit and system address is data port (i.e. cmd is high) and the value of index port is memory data register index (ex. f0h, f2h, f6h or f8h ? 2. the io32 is valid when the sd bus width is 32-bit and system address is data port (i.e. cmd is high) and the value of index port is memory data register index (ex. f0h, f2h, f6h or f8h) t1 t4 aen,sa ? t6 ? ? iow t2 ? sd ? t3 t8 t7 ? ? io16,io32 ? t5 note1.2 ,cmd dm9010 single chip ethernet controller with general processor interface preliminary 51 version: dm9010-ds-p03 apr. 28, 2005 10.3.5 external mii interface transmit timing symbol parameter min. typ. max. unit t 1 txen,txd[3 j 0] setup time 32 ns t 2 txen,txd[3 j 0] hold time 8 ns 10.3.6 external mii interface receive timing t1 t2 rxck rxer,rxdv ? ? rxd[3:0] symbol parameter min. typ. max. unit t 1 rxer, rxdv,rxd[3 j 0] setup time 5 ns t 2 rxer, rxdv,rxd[3 j 0] hold time 5 ns txck txen txd[3:0] t1 ? ? t2 dm9010 single chip ethernet controller with general processor interface preliminary 52 version: dm9010-ds-p03 apr. 28, 2005 10.3.7 mii management interface timing . % $ . % * 0 e s j w f e c z % . 5 5 5 5 5 . % * 0 e s j w f e c z f y f u s o b m . * * symbol parameter min. typ. max. unit t 1 mdc frequency 2 mhz t 2 mdio by dm9010 setup time 187 ns t 3 mdio by dm9010 hold time 313 ns t 4 mdio by external mii setup time 40 ns t 5 mdio by external mii hold time 40 ns 10.3.8 eeprom interface timing & & $ 4 & & $ , & & % 0 5 5 5 5 5 5 5 & & % * symbol parameter min. typ. max. unit t 1 eeck frequency 0.375 mhz t2 eecs setup time 500 ns t 3 eecs hold time 2166 ns t 4 eedo setup time 480 t 5 eedo hold time 2200 ns t 6 eedi setup time 8 ns t 7 eedi hold time 8 ns dm9010 single chip ethernet controller with general processor interface preliminary 53 version: dm9010-ds-p03 apr. 28, 2005 11. application notes 11.1 network interface signal routing place the transformer as close as possible to the rj-45 connector. place all the 50 ? resistors as close as possible to the dm9010 rxi ? and txo ? pins. traces routed from rxi ? and txo ? to the transformer should run in close pairs directly to the transformer. the designer should be careful not to cross the transmit and receive pairs. as always, vias should be avoided as much as possible. the network interface should be void of any signals other than the txo ? and rxi ? pairs between the rj-45 to the transformer and the transformer to the dm9010.. there should be no power or ground planes in the area under the network side of the transformer to include the area under the rj-45 connector. (refer to figure 11-4 and 11-5) keep chassis ground away from all active signals. the rj-45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2kv bypass capacitor. the band gap resistor should be placed as physically close as pins 25 and 26 as possible (refer to figure 11-1 and 11-2). the designer should not run any high-speed signal near the band gap resistor placement. 11.2 10base-t/100base-tx auto mdix application figure 11-1 auto mdix application dm9010 single chip ethernet controller with general processor interface preliminary 54 version: dm9010-ds-p03 apr. 28, 2005 11.3 10base-t/100base-tx ( non auto mdix transformer application ) figure 11-2 non auto mdix transformer application dm9010 single chip ethernet controller with general processor interface preliminary 55 version: dm9010-ds-p03 apr. 28, 2005 11.4 power decoupling capacitors davicom semiconductor recommends placing all the decoupling capac itors for all power supply pins as close as possible to the power pads of the dm9010 (the best placed distance is < 3mm from pin). the recommended decoupling capacitor is 0.1 ? f or 0.01 ? f, as required by the design layout. figure 11-3 power decoupling capacitors dm9010 single chip ethernet controller with general processor interface preliminary 56 version: dm9010-ds-p03 apr. 28, 2005 11.5 ground plane layout davicom semiconductor recommends a single ground plane approach to minimize emi. ground plane partitioning can cause increased emi emissions that could make the network interface card not comply with specific fcc regulations (part 15). figure 11-4 shows a recommended ground layout scheme. figure 11-4 ground plane layout dm9010 single chip ethernet controller with general processor interface preliminary 57 version: dm9010-ds-p03 apr. 28, 2005 11.6 power plane partitioning the power planes should be approximately illustrated in figure 11-5. figure 11-5 power plane partitioning dm9010 single chip ethernet controller with general processor interface preliminary 58 version: dm9010-ds-p03 apr. 28, 2005 11.7 magnetics selection guide refer to table 2 for transformer requirements. transformers, meeting these requirements, are available from a variety of magnetic manufacturers. designers should test and qualify all magnetics before using them in an application. the transformers listed in table 2 are electrical equivalents, but may not be pin-to-pin equivalents. manufacturer part number pulse engineering pe-68515, h1078, h1012, h1102 delta lf8200, lf8221x ycl 20pmt04, 20pmt05, ph163112 , ycl 0303 ph163539 *(auto mdix) halo tg22-3506nd, td22-3506g1, tg22-s010nd, tg22-s012nd tg110-s050n2 nano pulse inc. npi 6181-37, npi 6120-30, npi 6120-37 npi 6170-30 fil-mag pt41715 bel fuse s558-5999-01, s558-5999-w2 valor st6114, st6118 macronics hs2123, hs2213 bothhand ts6121c,16st8515,16st1086 table 2 11.8 crystal selection guide a crystal can be used to generate the 25mhz reference clock instead of an oscillator. the crystal must be a fundamental type, and series-resonant. connects to pins x1 and x2, and shunts each crystal lead to ground with a 22pf capacitor (see figure 11-6). 21 22 x1 x2 a gnd a gnd 22pf 25mhz 22pf figure 11-6 crystal circuit diagram dm9010 single chip ethernet controller with general processor interface preliminary 59 version: dm9010-ds-p03 apr. 28, 2005 11.9 application of reverse mii figure 11-7 note: when operating dm9010 at reverse mii mode, pin 78 is pulled high. at this application, the txclk , col and crs pins will be changed from input to output. dm9010 single chip ethernet controller with general processor interface preliminary 60 version: dm9010-ds-p03 apr. 28, 2005 12. package information lqfp 100l outline dimensions unit: inches/mm - ( % _ _ _ - % f u b j m ' d " " " 4 f b u j o h 1 m b o f ( % 4 f f % f u b j m ' ) % % & ) & ' d y c f symbol dimensions in inches dimensions in mm a 0.063 max. 1.60 max. a 1 0.004 0.002 0.1 0.05 a 2 0.055 0.002 1.40 0.05 b 0.009 0.002 0.22 0.05 c 0.006 0.002 0.15 0.05 d 0.551 0.005 14.00 0.13 e 0.551 0.005 14.00 0.13 e 0.020 bsc. 0.50 bsc. f 0.481 nom. 12.22 nom. gd 0.606 nom. 15.40 nom. hd 0.630 0.006 16.00 0.15 h e 0.630 0.006 16.00 0.15 l 0.024 0.006 0.60 0.15 l 1 0.039 ref. 1.00 ref. y 0.004 max. 0.1 max. 0 ~ 12 0 ~ 12 notes: 1. dimension d & e do not include resin fins. 2. dimension gd is for pc board surface mount pad pitch design reference only. 3. all dimensions are based on metric system. dm9010 single chip ethernet controller with general processor interface preliminary 61 version: dm9010-ds-p03 apr. 28, 2005 13. ordering information part number pin count package dm9010e 100 lqfp DM9010EP 100 lqfp(pb-free) disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrate d in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5646929 warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance a nd/or function. |
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